The packaging of microelectronic devices such as Integrated Circuits (ICs) and silicon-based sensors has been a major challenge since the invention of the microchip. While packaging is generally the last step in the overall fabrication process, the handling and packaging of individual circuits can be the most critical steps of all from considerations of cost and reliability.
As those skilled in the art will recognize, the individual IC chips/silicon-based sensors must be connected properly to outside leads and packaged in a way that is convenient for use in a larger circuit or system. The packaging must also be within a suitable medium which can protect the chip from the environment of its intended application. In most cases, this means that the surface of the device must be isolated from moisture and contaminants. The associated bonds and other elements must further be protected from corrosion and mechanical shock.
The approaches found in prior art for obtaining hermetically sealed electronic devices are disclosed, for example, in U.S. Pat. Nos. 4,995,149; 4,716,082; 4,464,419; 4,191,905; 3,755,720; and 3,669,734.
U.S. Pat. No. 4,995,149, issued to Arvikar et al., discloses a method for hermetically sealing electronic devices at the chip level of fabrication. In operation, glass is deposited through a mask and is deposited in the form of a surface film. Preheating and melting are also used to form the seal.
U.S. Pat. No. 3,755,720, issued to Kern, discloses an encapsulation procedure which passivates the surface of a semi-conductor device and encapsulates the surface and leads in glass. Again, encapsulation is done on the individual device at the chip level in the fabrication process.
U.S. Pat. No. 4,716,082, issued to Ahearn et al., discloses a glass-to-metal sealing process for manufacturing microcircuit chips. Again, the process provides for sealing at the chip level and further uses a pre-form.
U.S. Pat. No. 4,464,419, issued to Horn, discloses a process performed on individual devices to provide a quasi-hermetic covering of susceptible physical structures.
U.S. Pat. No. 4,191,905, issued to Yasuda et al., discloses a sealed housing for sub-miniature piezo-electric vibrators which accomplishes encapsulation of miniature piezo-electric resonators by bonding a metal cover plate to a glass substrate.
U.S. Pat. No. 3,755,730, issued to Kern, is directed to a glass encapsulated semi-conductor device. The patent discloses a technique for removing the glass covering from a bonding pad and simultaneously depositing a solderable metal film. As disclosed by Kern, the encapsulation procedure also occurs at the chip level after the wafer is diced.
Inherent in all packaging processes is the need that connection to the microelectronic micro devices must be made from the outside world, yet the devices themselves must be protected from the world environment because of the above-referenced damage and influences of water, vapor, chemical contamination, etc.
In the early days of Integrated Circuit technology, most microelectronic devices were packaged in metal headers. In this process, the devices were alloyed to the surface of the header, wire bonds were then made to the header posts, and a metal lid was welded over the device and wiring. This packaging method provided complete sealing of the unit from the outside environment and was often referred to as a "hermetically sealed" device. After the chip was mounted on the header and bonds were made to the posts, the header cap could be welded shut in a controlled environment, such as, for example, an inert gas, which maintains the device in a prescribed atmosphere.
Because of the numerous lead connections involved, most integrated circuits are now mounted in packages 10 similar to that shown in FIG. 1. As those skilled in the art will recognize, this is one form of a Dual In-line Package (DIP), in which connectors or leads 12 are brought out along two sides of the package 10. After mounting the chip on a stamped metal lead frame 14 and forming the contacts, the package 10 is formed by applying a ceramic or plastic case 16 and trimming away the unwanted parts of the lead frame 14. Wire leads 18, usually gold or aluminum, are used to attach the chip 20 to lead frame 14.
In addition to the sealed metal containers identified above, ceramic, ceramic packages and molded epoxy resin bodies have also been utilized. In all cases, however, the conductors needed to make the connection between the outside world and the microelectronic device must still pass out of the electronic package. The interface between the packaging material and the connecting wires or leads have often been the avenue of contamination for the packaged devices, thus limiting their lifetime in the sometimes harsh environments of certain applications.
The most successful interface seal used to date has been the metal-glass seal in the hermetic package when the glasses are chosen to match the thermal expansion characteristics of the wire interconnect. The conventional hermetic package, while effective in the harshest environments, however, is nonetheless expensive and bulky in order to accommodate the metal seals in the regions of glass-metal seals.
In addition, the conventional hermetic package as well as other packaging schemes known to date, have utilized lead frames as shown in FIG. 1 which allow internal connections with bonding wires between the interconnect lead frames and the microelectronic chips or sensors. The need for this intermediate stage between the microchip and the electrical connection to the system has, understandably, increased costs, assembly, handling and production time. In addition, this intermediate step is highly labor intensive and often requires exportation of the microchips to manufacturing facilities for assembly into packages. This process further increases the risk of failures due to improper handling and lack of assembly-room environmental controls.
Consequently, there has developed a need for a packaging scheme that allows hermetic sealing and encapsulation of microelectronic devices to be done at the wafer level in order to reduce costs, improve reliability and enable assembly at a higher production rate with less human labor involvement. Such a packaging scheme should be capable of being completed in the same facility as that used to fabricate the microelectronic device, i.e., microchip or silicon-based sensor.